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? semiconductor components industries, llc, 2014 december, 2014 ? rev. 0 1 publication order number: NCP81253/d NCP81253 5 v mosfet driver compatible with single-phase imvp8 controllers the NCP81253 is a high performance dual mosfet gate driver in a small 2 mm x 2 mm package, optimized to drive the gates of both high?side and low?side power mosfets in a synchronous buck converter. the driver outputs can be placed into a high?impedance state via the tri?state pwm and en inputs. the NCP81253 comes packaged with an integrated boost diode to minimize external components. a vcc uvlo function guarantees the outputs are low when the supply voltage is low. features ? space?ef ficient 2 mm x 2 mm dfn8 thermally?enhanced package ? vcc range of 4.5 v to 5.5 v ? internal bootstrap diode ? 5 v 3?stage pwm input ? diode braking capability via en mid?state ? adaptive anti?cross conduction circuit protects against cross?conduction during fet turn?on and turn?off ? output disable control turns off both mosfets via enable pin ? vcc undervoltage lockout ? these devices are pb?free, halogen?free/bfr?free and are rohs compliant typical applications ? power solutions for notebook and desktop systems device package shipping ? ordering information NCP81253mntbg dfn8 (pb?free) 3000 / tape & reel dfn8 case 506aa marking diagram www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. cg = specific device code m = date code = pb?free package 1 2 3 4 5 6 7 8 bst pwm sw vcc en drvh drvl gnd pinout diagram (note: microdot may be in either location) flag 9 cgm 1 1 (top view)
NCP81253 www. onsemi.com 2 figure 1. block diagram pwm logic anti?cross conduction vcc vcc en uvlo sw gnd bst drvh drvl vcc table 1. pin function description pin no. pin name description 1 bst floating bootstrap supply pin for the high?side gate driver. connect the external bootstrap capacitor between this pin and sw. 2 pwm control input: pwm = high drvh is high, drvl is low. pwm = mid drvh and drvl are low. pwm = low drvh is low, drvl is high. 3 en 3?state input: en = high driver is enabled; normal pwm operation. en = mid driver is enabled; drvh and drvl are low (body diode braking). en = low driver is disabled. 4 vcc power supply input. connect a bypass capacitor from this pin to ground. 5 drvl low?side gate drive output. connect to the gate of the low?side mosfet. 6 gnd bias and reference ground. all signals are referenced to this node. 7 sw switch node. connect this pin to the source of the high?side mosfet and drain of the low?side mosfet. 8 drvh high?side gate drive output. connect to the gate of the high?side mosfet. 9 flag thermal flag. there is no electrical connection to the ic. connect to the ground plane.
NCP81253 www. onsemi.com 3 table 2. absolute maximum ratings rating symbol min max main supply voltage (note 1) v cc ?0.3 v 6.5 v bootstrap supply voltage bst ?0.3 v wrt/sw 35 v wrt/gnd 40 v ( 50 ns) wrt/gnd 6.5 v wrt/sw switch node voltage sw ?5 v ?10 v ( 200 ns) 35 v 40 v ( 50 ns) high?side driver output drvh ?0.3 v wrt/sw ?2 v ( 200 ns) wrt/sw bst + 0.3 v wrt/sw low?side driver output drvl ?0.3 v ?5 v ( 200 ns) vcc + 0.3 v drvh/drvl control input, enable pin pwm, en ?0.3 v 6.5 v ground gnd 0 v 0 v storage temperature range tstg ?55 c 150 c operating junction temperature range tj ?40 c 150 c moisture sensitivity level msl 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristis and application information for safe operating area. table 3. thermal characteristics rating symbol value unit thermal characteristics, dfn8, 2x2 mm (note 2) thermal resistance, junction?to?air r ja 119 c/w 2. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. table 4. operating ranges (note 3) rating symbol min max unit input voltage vcc 4.5 5.5 v ambient temperature t a ?40 100 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 3. refer to electrical characteristis and application information for safe operating area. table 5. electrical characteristics vcc = 4.5 v to 5.5 v, vbst?swn = 4.5 v to 5.5 v, bst = 4.5 v to 30 v, sw = 0 v to 21 v; for typical values t a = 25 c, for min/max values t a = ?40 c to 100 c; unless otherwise noted. (notes 4, 5) parameter test conditions symbol min typ max unit supply voltage vcc operation voltage vcc 4.5 5.5 v undervoltage lockout vcc start threshold vcc rising v uvlo 3.8 4.35 4.5 v vcc uvlo hysteresis v uvlo_hys 150 200 250 mv supply current shutdown mode icc + ibst, en = gnd i shutdown 1 20 a normal mode icc + ibst, en = 5 v, pwm = 400 khz no load on driver outputs. i normal 1.6 ma standby current 1 icc + ibst, en = 5 v, pwm = 0 v i standby 0.9 ma 4. refer to absolute maximum ratings and application information for safe operating area. 5. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
NCP81253 www. onsemi.com 4 table 5. electrical characteristics vcc = 4.5 v to 5.5 v, vbst?swn = 4.5 v to 5.5 v, bst = 4.5 v to 30 v, sw = 0 v to 21 v; for typical values t a = 25 c, for min/max values t a = ?40 c to 100 c; unless otherwise noted. (notes 4, 5) parameter unit max typ min symbol test conditions bootstrap diode forward voltage vcc = 5 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input pwm input high pwm hi 3.4 v pwm mid?state pwm mid 1.3 2.7 v pwm input low pwm lo 0.7 v high?side driver output impedance, sourcing current vbst ? vsw = 5 v 0.9 1.7 output impedance, sinking current vbst ? vsw = 5 v 0.7 1.7 drvh rise time vcc = 5 v, c load = 3 nf, vbst?vsw = 5 v, drvh?sw = 90% to 10% tr drvh 16 25 ns drvh fall time vcc = 5 v, c load = 3 nf , vbst?vsw = 5 v, drvh?sw = 90% to 10% tf drvh 11 18 ns drvh turn?of f propagation delay c load = 3 nf, pwm = pwm lo to drvh = 90% tpdl drvh 10 18 30 ns drvh turn?on propagation delay c load = 3 nf, drvl = 1 v to drvh?sw = 10% tpdh drvh 10 15 40 ns sw pull?down resistance sw to gnd 45 k drvh pull?down resistance drvh to sw 45 k low?side driver output impedance, sourcing current vcc = 5 v 0.9 1.7 output impedance, sinking current vcc = 5 v 0.4 0.8 drvl rise time vcc = 5 v, c load = 3 nf, vbst?vsw = 5 v, drvl = 90% to 10% tr drvl 11 25 ns drvl fall time vcc = 5 v, c load = 3 nf , vbst?vsw = 5 v, drvl = 90% to 10% tf drvl 8 15 ns drvl turn?of f propagation delay c load = 3 nf, pwm = pwm hi to drvl = 90% tpdl drvl 10 15 30 ns drvl turn?on propagation delay c load = 3 nf, drvh?sw = 1 v to drvl = 10% tpdh drvl 5 8 25 ns drvl pull?down resistance drvl to gnd, vcc = gnd 45 k en input enable voltage high en hi 3.3 v enable voltage mid en mid 1.35 1.8 v enable voltage low en lo 0.6 v input bias current ?1.0 1.0 a en high propagation delay time pwm = 0 v, en going from 0 v to en hi to drvl rising to 10% tpd en_hi 20 40 ns switch node sw node leakage current 20 a 4. refer to absolute maximum ratings and application information for safe operating area. 5. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
NCP81253 www. onsemi.com 5 typical characteristics figure 2. standby current vs. temperature (v cc = 5 v, en = 5 v, pwm = 0 v) figure 3. supply current vs. switching frequency (v cc = 5 v, c load = 3 nf) ambient temperature ( c) switching frequency (khz) 80 100 60 40 20 0 ?20 ?40 0.7 0.8 0.9 1.0 1.1 1.2 900 800 700 500 400 300 200 100 0 5 10 15 20 25 35 40 figure 4. v cc uvlo vs. temperature (en = 5 v) figure 5. pwm low/mid thresholds vs. temperature (v cc = 5 v) ambient temperature ( c) ambient temperature ( c) 80 60 40 100 20 0 ?20 ?40 3.7 3.9 4.1 4.3 4.5 4.7 100 80 60 40 20 0 ?20 ?40 0.5 0.7 0.9 1.1 1.3 1.5 figure 6. pwm mid/high thresholds vs. temperature (v cc = 5 v) figure 7. enable low/mid thresholds vs. temperature (v cc = 5 v) ambient temperature ( c) ambient temperature ( c) 80 60 40 100 20 0 ?20 ?40 2.5 2.7 2.9 3.1 3.3 3.5 100 80 60 40 20 0 ?20 ?40 0.5 0.7 0.9 1.1 1.3 1.5 standby current (ma) supply current (ma) vcc uvlo (v) pwm threshold, low/mid (v) pwm threshold mid/high (v) pwm threshold low/mid (v) 600 1000 30 rising falling rising falling rising falling rising falling
NCP81253 www. onsemi.com 6 typical characteristics figure 8. enable mid/high thresholds vs. temperature (v cc = 5 v) figure 9. drvh rise/fall times vs. temperature (v bst ? v sw = 5 v, c load = 3 nf) ambient temperature ( c) ambient temperature ( c) 80 60 40 100 20 0 ?20 ?40 2.6 2.8 3.0 3.2 3.4 80 60 100 40 20 0 ?20 ?40 0 5 10 15 20 25 figure 10. drvl rise/fall times vs. temperature (v cc = 5 v, c load = 3 nf) figure 11. dead times vs. temperature (v cc = 5 v, c load = 3 nf) ambient temperature ( c) ambient temperature ( c) 80 60 40 100 20 0 ?20 ?40 0 5 10 15 20 25 100 80 60 40 20 0 ?20 ?40 0 5 10 15 20 25 figure 12. drvh/drvl prop delays vs. temperature (v cc = 5 v, c load = 3 nf) figure 13. enable mid prop delays vs. temperature (v cc = 5 v, c load = 3 nf) ambient temperature ( c) ambient temperature ( c) 80 60 40 100 20 0 ?20 ?40 0 5 10 15 20 25 100 80 60 40 20 0 ?20 ?40 10 15 20 25 30 35 40 50 pwm threshold mid/high (v) drvh rise/fall times (ns) drvh rise/fall times (ns) drvl rise/fall times (ns) drvh/drvl prop delays (ns) enable mid prop delays (ns) rising falling rise time fall time rise time fall time tpdhdrvh tpdhdrvl tpdldrvh tpdldrvl high?to?mid mid?to?high 45
NCP81253 www. onsemi.com 7 bst pwm en vcc drvh pad drvl gnd sw 5v_power vin pwm dron vccp q1 ntmfs4821n q2 ntmfs4851n q3 r1 1.02 r2 0.0 c2 c1 r3 0.0 r4 2.2 c3 2700 pf l 235 nh c4 c5 c6 c7 NCP81253 figure 14. application circuit 1 f 0.1 f ntmfs4851n 4.7 f 4.7 f 4.7 f 390 f pwm drvl drvh?sw 90% 10% 1 v 10% 90% 1 v 10% 90% 90% 10% figure 15. gate timing diagram tf drvl tr drvh tpdl drvl tpdh drvh tf drvh tr drvl tpdh drvl tpdl drvh
NCP81253 www. onsemi.com 8 pwm en drvh drvl figure 16. pwm/en logic diagram applications information the NCP81253 gate driver is a single?phase mosfet driver designed for driving n?channel mosfets in a synchronous buck converter topology. the NCP81253 is designed to work with single?phase imvp8 controllers such as the ncp81206. low?side driver the low?side driver is designed to drive a ground?referenced low?r ds(on) n?channel mosfet. the voltage supply for the low?side driver is internally connected to the vcc and gnd pins. high?side driver the high?side driver is designed to drive a floating low?r ds(on) n?channel mosfet. the gate voltage for the high?side driver is developed by a bootstrap circuit referenced to the sw pin. the bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor . when the NCP81253 is starting up, the sw pin is held at ground, allowing the bootstrap capacitor to charge up to vcc through the bootstrap diode. when the pwm input is driven high, the high?side driver will turn on the high?side mosfet using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the sw pin rises. when the high?side mosfet is fully turned on, sw will settle to vin and bst will settle to vin + vcc (excluding parasitic ringing). bootstrap circuit the bootstrap circuit relies on an external charge storage capacitor (c bst ) and an integrated diode to provide current to the high?side driver. a multi?layer ceramic capacitor (mlcc) with a value greater than 100 nf should be used for c bst . power supply decoupling the NCP81253 can source and sink relatively large currents to the gate pins of the mosfets. in order to maintain a constant and stable supply voltage, a low?esr capacitor should be placed near the vcc and gnd pins. a mlcc between 1 f and 4.7 f is typically used. undervoltage lockout drvh and drvl are low until vcc reaches the vcc uvlo threshold, typically 4.35 v. once vcc reaches this threshold, the pwm signal will control drvh and drvl. there is a 200 mv hysteresis on vcc uvlo. there are pull?down resistors on drvh, drvl and sw to prevent the gates of the mosfets from accumulating enough charge to turn on when the driver is powered off. three?state en input placing en into a logic?high and logic?low will turn the driver on and off, respectively, as long as vcc is greater than the uvlo threshold. the en threshold limits are specified
NCP81253 www. onsemi.com 9 in the electrical characteristics table in this datasheet. setting the voltage on en to a mid?state level will pull both drvh and drvl low. refer to table 6 for the en/pwm logic table. setting en to the mid?state level can be used for body diode braking to quickly reduce the inductor current. by turning the ls fet off and having the current conduct through the ls fet body diode, the voltage at the switch node will be at a greater negative potential compared to having the ls fet on. this greater negative potential on switch node allows there to be a greater voltage across the output inductor, since the opposite terminal of the inductor is connected to the converter output voltage. the larger voltage across the inductor causes there to be a greater inductor current slew rate, allowing the current to decrease at a faster rate. three?state pwm input switching pwm between logic?high and logic?low states will allow the driver to operate in continuous conduction mode as long as vcc is greater than the uvlo threshold and en is high. the threshold limits are specified in the electrical characteristics table in this datasheet. refer to figure 15 for the gate timing diagrams and table 6 for the en/pwm logic table. when pwm is set above pwm hi , drvl will first turn off after a propagation delay of tpdl drvl . to ensure non?overlap between drvl and drvh, there is a delay of tpdh drvh from the time drvl falls to 1 v, before drvh is allowed to turn on. when pwm falls below pwm lo , drvh will first turn off after a propagation delay of tpdl drvh . to ensure non?overlap between drvh and drvl, there is a delay of tpdh drvl from the time drvh ? sw falls to 1 v, before drvl is allowed to turn on. when pwm enters the mid?state voltage range (and thereby exiting the logic high or logic low states), both drvh and drvl are pulled low for the non?overlap delay (tpdh). if pwm is still in the mid?state at the conclusion of the non?overlap delay, both dr vh and drvl will remain in the off states. to minimize power consumption when the NCP81253 is in a disabled state, the internal voltage rails that determine the low/mid/high pwm logic states are shut down when en is low. when en is brought high (while vcc is above the uvlo threshold), the pwm internal voltage rails are brought up, but require some time to rise to their proper levels. to prevent a pwm signal from being interpreted incorrectly during this time, there is a delay from en rising to the driver responding to pwm signals, which is set at a typical value of 50 s. table 6. en/pwm logic table en pwm drvh drvl low x low low high low low high high mid low low high high high low mid low low low mid mid low low mid high low low thermal considerations as power in the NCP81253 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the NCP81253 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the NCP81253 can handle is given by: p d(max) t j(max) t a r ja (eq. 1) since t j is not recommended to exceed 150 c, the NCP81253, soldered on to a 645 mm 2 copper area, using 1 oz. copper and fr4, can dissipate up to 1.05 w when the ambient temperature (t a ) is 25 c. the power dissipated by the NCP81253 can be calculated from the following equation: p d vcc (n hs qg hs
n ls qg ls ) f
i standby (eq. 2) where n hs and n ls are the number of high?side and low?side fets, respectively, qg hs and qg ls are the gate charges of the high?side and low?side fets, respectively and f is the switching frequency of the converter.
NCP81253 www. onsemi.com 10 package dimensions dfn8 2x2 case 506aa issue e ??? ??? a d e b c 0.15 pin one 2x reference 2x top view side view bottom view a l (a3) d2 e2 c c 0.15 c 0.10 c 0.08 note 4 a1 seating plane e/2 e 8x k note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k l 0.25 0.35 1 4 8 5 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.50 8x dimensions: millimeters 0.30 pitch 8x 1 package outline recommended l1 detail a l optional constructions l ??? 0.10 0.30 ref 0.90 1.30 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81253/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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